(a). Field of the Invention
The present invention relates to a flash memory and a method for manufacturing the same, and more particularly, to a flash memory and a method for manufacturing the same in which the flash memory is driven by a low voltage identical to that needed to drive a logic circuit.
(b). Description of the Related Art
Flash memory has many of the benefits of EPROMs (erasable programmable read only memories) and EEPROMs (electrically erasable programmable read only memories) including erasability and reprogrammability. In addition, the manufacture of flash memory is simple and relatively inexpensive, and a small chip size may be realized.
Further, flash memory is non-volatile semiconductor memory in that data stored in it is not destroyed, even without power or backup batteries. However, the ease with which writing and erasing is electrically performed gives flash memory the characteristics of RAM (random access memory). Accordingly, flash memory is being used in memory cards and memory devices that are replacing hard disks in portable office automation systems.
The programming of data in flash memory is realized by the injection of hot electrons. That is, if hot electrons are generated in a channel by a difference in potential between a source and a drain, some of these electrons that obtain an energy greater than that of a potential barrier between polycrystalline silicon realizing a gate and an oxidation layer move to a floating gate by a high electric field trapped at a control gate to be stored.
Since hot electrons cause a degradation of performance in a typical MOS element, the elements are designed to minimize this effect. However, flash memory is designed to generate hot electrons.
Conventional flash memory will be described with reference to FIG. 1.
A gate oxide layer 2 is formed on a portion of an element region of a semiconductor substrate 1. Formed on the gate oxide layer 2 is a floating gate 3, which is made of polysilicon. The floating gate 3 is fully encased and acts as an electronic storage node. Further, a dielectric layer 4 is formed on the floating gate 3. The dielectric layer 4 is realized through a layered structure of an oxide layer, a nitride layer, and then again an oxide layer. A control gate 5, made from polysilicon, is formed on the dielectric layer 4, and performs the function of a gate in a typical MOS transistor.
Provided along side walls of a gate, comprised of the gate oxide layer 2, the floating gate 3, the dielectric layer 4, and the control gate 5, is a spacer 7. Further, an LDD (lightly doped drain) 6, doped at a low concentration with impurities of an opposite conductivity as the semiconductor substrate 1, is formed under the spacer 7 on the semiconductor substrate 1. Formed on the semiconductor substrate 1 contacting the LDD 6 and extending away from the spacer 7 and the elements of the gate is a source/drain region 8. The source/drain region 8 is doped at a high concentration with impurities of the same conductivity as the LDD 6.
With reference to FIG. 2, in the conventional flash memory structured as in the above, electrons flow to the floating gate from the semiconductor substrate in accordance with the operation of the element, as a result of F-N (Fowler-Nordheim) tunneling. At this time, a current density JFN is as shown in Equation 1 below.JFN=αFNEOX2exp[βFN/EOX]  [Equation 1]where αFN and βFN are respectively functional constants of an effective mass and a barrier height, and EOX is an electric field on both ends of an oxidation layer.
With the conventional flash memory, the drive voltage of the element is dependent on the thickness of the oxidation layer, and generally has a programming voltage of between 5 and 8V. However, since the logic circuit is driven at a different voltage of approximately 3.3V, it is not possible to provide both the flash memory and logic circuit on a single chip.